搜索结果: 1-14 共查到“知识库 信息处理技术 VLSI”相关记录14条 . 查询时间(0.134 秒)
Hardware Oriented Algorithm Analysis and Modification for High Definition AVS Video Encoder VLSI Implementation
Hardware Oriented Algorithm Analysis Modification High Definition AVS Video Encoder
2010/6/30
In AVS video coding standard, some algorithms consume huge computation with relatively little coding performance contribution, and some algorithms create data dependencies that are harmful for efficie...
Hardware Oriented Algorithm Analysis and Modification for High Definition AVS Video Encoder VLSI Implementation
Hardware Oriented Algorithm Analysis Modification High Definition AVS Video Encoder
2010/6/30
In AVS video coding standard, some algorithms consume huge computation with relatively little coding performance contribution, and some algorithms create data dependencies that are harmful for efficie...
Efficient Macroblock Pipeline Structure in High Definition AVS Video Encoder VLSI Architecture
Efficient Macroblock Pipeline Structure AVS Video Encoder VLSI Architecture
2010/6/30
In traditional four-stage pipeline structures for H.264 video encoder hardware implementation, rate distortion optimization (RDO) based mode decision was turned off, and
dual-port or ping-pang on-chi...
High Throughput VLSI Architecture for Multiresolution Motion Estimation in High Definition AVS Video Encoder
VLSI Architecture Multiresolution Motion Estimation Video Encoder
2010/6/30
This paper proposes a hardware friendly multiresolution motion estimation algorithm and VLSI architecture for high definition MPEG-like video encoder hardware implementation. By parallel searching and...
数字电视标准DMB-T高速LDPC译码器VLSI设计
数字电视广播地面传输标准 修正最小和算法 半并行译码器
2009/7/10
在我国的数字电视广播地面传输标准DMB-T中，使用了准循环非规则LDPC码作为前向纠错编码。针对此标准中LDPC码的特点，采用修正最小和译码算法，设计了一种半并行结构实时译码器，可实现DMB-T中三种不同码率下的LDPC译码，并有效地实现了硬件结构复用。与其他设计方案相比较，减少了RAM块的数量一半以上，全局布线难度也大大降低。整个设计在Stratix II FPGA上进行了综合验证。当译码迭代次...
VLSI冗余单元最优分配的遗传算法求解
遗传算法 成品率 备用单元
2009/5/8
随着VLSI芯片面积的增加和电路复杂性的增强,芯片的成品率受制造缺陷影响的概率逐渐增加。为了解决这一问题,人们将容错技术结合入集成电路设计中。要使一个系统具有较强的容错能力,必须给系统提供一定量冗余单元。本文利用遗传算法有效地解决了使系统成品率达到最大的冗余单元最优分配问题。
适合硬件实现的JPEG2000码率控制算法及其VLSI结构设计
图像处理 图像压缩 率控制
2009/1/22
为了简化硬件实现的复杂度和降低存储量，提出一种采用码率预分配的JPEG2000码率控制算法，并给出相应的VLSI结构设计．原始图像经过小波变换和量化后，对EBCOT码块的有效比特平面进行独立熵估计，计算出所有码块的估计熵总和．依据每个码块的估计熵在所有码块的估计熵总和中所占的比例，指导分配每个码块的码率，EBCOT编码器根据分配到的码率实时截断码流和编码通道，减少了T1编码的时间．码块经过T1编码...
A Novel VLSI Architecture of Motion Compensation for Multiple Standards
VLSI Architecture Motion Compensation Multiple Standards
2008/12/31
Motion compensation (MC) is one of the most important technologies capable of removing the temporal redundancy and widely adopted by the main video standards. From the older MPEG-2 to the latest H.264...
An Efficient VLSI Architecture for Motion Compensation of AVS HDTV Decoder
VLSI Architecture Motion Compensation AVS HDTV Decoder
2006/12/31
An Efficient VLSI Architecture for Motion Compensation of AVS HDTV Decoder.
An Efficient VLSI Architecture of VLD for AVS HDTV Decoder
VLSI Architecture VLD AVS HDTV Decoder
2006/12/31
!aIn this paper, we present a VLSI design of Variable Length Code Decoder for AVS video standard. As a co-processor of a RISC CPU, the design can decode Fixed Length Code, unsigned or signed k-th Exp-...
An Implemented VLSI Architecture of Inverse Quantizer for AVS HDTV Video Decoder
VLSI Architecture Inverse Quantizer AVS HDTV Video Decoder
2005/12/31
AVS is Chinese new audio and video coding standard. A pipeline-based architecture of inverse quantizer for AVS video standard is proposed in this paper. Due to using one-pass processing for Run Length...
Improved FFSBM Algorithm and Its VLSI Architecture for Variable Block Size Motion Estimation of H.264,
Improved FFSBM Algorithm VLSI Architecture Variable
2005/12/31
The video coding standard H.264/AVC has adopted variable block size motion estimation to improve coding efficiency, which has brought heavy computation burden.The FFSBM (fast full search block matchin...
An Efficient VLSI Architecture for MC Interpolation in AVC Video Coding
VLSI Architecture MC Interpolation AVC Video Coding
2004/12/31
Video Coding (AVC) has employed a 6-tap interpolation FIR filter in its motion compensation (MC) part for high coding efficiency. But it is accompanied by increasing the complexity in calculation and ...
An Efficient VLSI Architecture of the Sample Interpolation for MPEG-4 Advanced Simple Profile
Efficient VLSI Architecture the Sample Interpolation MPEG-4 Advanced Simple Profile
2004/12/31
Sample interpolation which has a computationally expensive finite impulse response (FIR) digital filter is one of the key modules in MPEG-4 Advanced Simple Profile (ASP). Normal FIR architectures have...