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Design and Evaluation of an L-Band Current-Mode Class-D Power Amplifier Integrated Circuit
power amplifier mixer integrated circuit model efficiency
2014/12/8
Power amplifiers (PAs) convert energy from DC to high frequencies in all radio and microwave transmitter systems be they wireless base stations, handsets, radars, heaters, and so on. PAs are the domin...
Multilevel Optical Modulator with PLC and LiNbO 3 Hybrid Integrated Circuit
Electro-optical devices Waveguide modulators
2011/5/26
Optical modulators with a hybrid configuration of silica-PLCs and LiNbO 3 phase modulators are promising for advanced multilevel modulation formats. Modulators for OFDM-QPSK, 64QAM, and a selectable f...
Large-Scale Photonic Integrated Circuit for Multi-Format Regeneration and Wavelength Conversion
Integrated optics devices Nonlinear optical signal processing
2011/5/22
We demonstrate a large-scale silica-on-silicon photonic integrated circuit with 4 hybridly integrated SOAs for multi-format regeneration and wavelength conversion. Power penalty improvement up to 1.5d...
Silicon Photonics Technologies for Monolithic Electronic-Photonic Integrated Circuit Applications
Integrated optics devices Optoelectronics Semiconductors
2011/5/22
By leveraging on the wealth of Si-CMOS technology know-how and the largely available infrastructures, the fundamental photonic device building blocks and circuit integration platform,essential for the...
10 Channel, 100Gbit/s per Channel, Dual Polarization, Coherent QPSK, Monolithic InP Receiver Photonic Integrated Circuit
10 Channel 100Gbit/s per Channel Dual Polarization Coherent QPSK Monolithic InP Receiver Photonic Integrated Circuit
2011/5/20
A 10 channel, dual polarization, monolithically integrated, coherent QPSK receiver on InP operating at 100Gbit/s per channel is demonstrated.
Photonic Integrated Circuit Switch Matrix and Waveguide Delay Lines for Optical Packet Synchronization
Photonic Integrated Circuit Switch Matrix Waveguide Delay Lines Optical Packet Synchronization
2008/8/4
The first integrated synchronizer is demonstrated using silica delays coupled to an InP switch. Error-free performance is presented for delays of 0, 2.96, 6.56 and 9.52ns.