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Improved FFSBM Algorithm and Its VLSI Architecture for Variable Block Size Motion Estimation of H.264,
Improved FFSBM Algorithm VLSI Architecture Variable
2005/12/31
The video coding standard H.264/AVC has adopted variable block size motion estimation to improve coding efficiency, which has brought heavy computation burden.The FFSBM (fast full search block matchin...
An Efficient VLSI Architecture for MC Interpolation in AVC Video Coding
VLSI Architecture MC Interpolation AVC Video Coding
2004/12/31
Video Coding (AVC) has employed a 6-tap interpolation FIR filter in its motion compensation (MC) part for high coding efficiency. But it is accompanied by increasing the complexity in calculation and ...
An Efficient VLSI Architecture of the Sample Interpolation for MPEG-4 Advanced Simple Profile
Efficient VLSI Architecture the Sample Interpolation MPEG-4 Advanced Simple Profile
2004/12/31
Sample interpolation which has a computationally expensive finite impulse response (FIR) digital filter is one of the key modules in MPEG-4 Advanced Simple Profile (ASP). Normal FIR architectures have...
An Efficient VLSI Implementation for MC Interpolation of AVS Standard
VLSI Implementation MC Interpolation AVS Standard
2004/12/31
Advance Video Coding standard (AVS) [1] is the standard for compression and decompression in digital audio and video multimedia.The AVS Working Group was approved by the Science and Technology Departm...