搜索结果: 91-105 共查到“知识库 计算机工程”相关记录1101条 . 查询时间(3.965 秒)
Multiparty Key Exchange, Efficient Traitor Tracing, and More from Indistinguishability Obfuscation
Multiparty Key Exchange Effi cient Traitor Tracing
2015/8/5
Our traitor tracing system is fully collusion resistant with short ciphertexts, secret keys,
and public key. Ciphertext size is logarithmic in the number of users and secret key size is
independent ...
Low Overhead Broadcast Encryption from Multilinear Maps
Multilinear Maps Broadcast Encryption
2015/8/5
We use multilinear maps to provide a solution to the long-standing problem of public-key
broadcast encryption where all parameters in the system are small. In our constructions,
ciphertext overhead,...
Fully Key-Homomorphic Encryption, Arithmetic Circuit ABE, and Compact Garbled Circuits
Arithmetic Circuit ABE Compact Garbled Circuits
2015/8/5
We construct the rst (key-policy) attribute-based encryption (ABE) system with short
secret keys: the size of keys in our system depends only on the depth of the policy circuit,
not its size. Our c...
Function-Private Subspace-Membership Encryption and Its Applications
Function privacy functional encryption
2015/8/5
Boneh, Raghunathan, and Segev (CRYPTO '13) have recently put forward the notion of function privacy and applied it to identity-based encryption, motivated by the need for providing predicate privacy i...
Mental abacus (MA) is a system for performing rapid and precise arithmetic by manipulating a mental
representation of an abacus, a physical calculation device. Previous work has speculated that MA is...
为了在保证胚胎电子系统可靠性的前提下降低系统的硬件消耗，提出一种新型的基因存储结构——部分基因循环存储，细胞只存储阵列的部分基因，通过细胞内、细胞间的基因循环、非循环移位实现阵列的功能分化和自修复，自修复过程中基因存储内容根据故障细胞数目进行自主更新。该存储结构中基因备份数目可由设计者根据系统可靠性和硬件消耗要求设置，不受阵列中空闲资源数目的限制。理论分析和仿真实验表明，该新型存储结构不仅实现了胚...
A Dynamically Configurable Discrete Event Simulation Framework for Many-Core System-on-Chips
Many-core heterogeneous processors Processor Simulator Mhetero
2015/1/20
Industry trends indicate that many-core heterogeneous processors will be the next-generation answer to Moore's law and reduced power consumption. Thus, both academia and industry are focused on the ch...
专网组播应用设计与安全策略
专网 组播设计 安全策略
2015/1/16
介绍了测通专网主要拓扑结构、业务应用情况，分析研究了组播关键技术、特点及面临的安全问题，对专网的组播协议选择、路由设计、组播安全策略设置方面提出了具体的设计方案和建议。
损耗均衡影响智能电能表中闪存固态存储系统的寿命和性能.为了提高系统寿命和性能,本文提出了一种有效减小最大擦除次数差的损耗均衡设计.该设计根据位置指针所指物理块的相对擦除次数差来决定损耗均衡是否需要启动和损耗均衡需要的物理块地址.实验结果表明,该设计相比于已有的损耗均衡方法,能有效减小最大擦除次数差,减小擦除次数方差,有效降低损耗不均衡程度.本文还对影响损耗均衡程度的触发阈值进行了分析与讨论,得出了...
Electronic Discovery: The Basics
electronic discovery bankruptcy Electronic Discovery Reference Model (EDRM) electronically stored information
2014/12/20
This article is the first in a series about electronic discovery in bankruptcy. This article will cover the basics of electronic discovery, including history, rules and resources. Future articles will...
New E-Discovery Sources, Tips and Tactics; Social Media and E-Discovery
e-discovery social media legal research email mobile apps for e-discovery
2014/12/20
Websites and other sources for researching e-discovery cases; email as evidence; mobile apps for e-discovery; social media archiving and compliance; handling social media as electronically stored info...
Enhanced Search And Efficient Storage Using Data Compression In Nand Flash Memories
Nand Flash Search data deduplication MISR
2014/12/8
NAND flash memories are popular due to their density and lower cost. However, due to serial access, NAND flash memories have low read and write speeds. As the flash sizes increase to 64GB and beyond, ...
Heterogeneous Graphene Nanoribbon-CMOS Multi-State Volatile Random Access Memory Fabric
Graphene GNTRAM heterogeneous memory multistate memory graphene nanoribbons
2014/12/8
CMOS SRAM area scaling is slowing down due to several challenges faced by transistors at nanoscale such as increased leakage. This calls for new concepts and technologies to overcome CMOS scaling limi...
Low Cost Dynamic Architecture Adaptation Schemes for Drowsy Cache Management
Drowsy cache Architecture Adaptation Low Power Leakage Reduction Dynamic Schemes
2014/12/8
Energy consumption and speed of execution have long been recognized as conflicting requirements for processor design. In this work, we have developed a low-cost dynamic architecture adaptation scheme ...
Design of an Open-Source SATA Core for Virtex-4 FPGAs
SATA FPGA Virtex-4 Hardware Storage High Speed Serial I/O
2014/12/8
Many hard drives manufactured today use the Serial ATA (SATA) protocol to communicate with the host machine, typically a PC. SATA is a much faster and much more robust protocol than its predecessor, A...