搜索结果: 1-4 共查到“数据处理 VLSI”相关记录4条 . 查询时间(0.197 秒)
A Novel VLSI Architecture of Motion Compensation for Multiple Standards
VLSI Architecture Motion Compensation Multiple Standards
2008/12/31
Motion compensation (MC) is one of the most important technologies capable of removing the temporal redundancy and widely adopted by the main video standards. From the older MPEG-2 to the latest H.264...
An Efficient VLSI Architecture for Motion Compensation of AVS HDTV Decoder
VLSI Architecture Motion Compensation AVS HDTV Decoder
2006/12/31
An Efficient VLSI Architecture for Motion Compensation of AVS HDTV Decoder.
Improved FFSBM Algorithm and Its VLSI Architecture for Variable Block Size Motion Estimation of H.264,
Improved FFSBM Algorithm VLSI Architecture Variable
2005/12/31
The video coding standard H.264/AVC has adopted variable block size motion estimation to improve coding efficiency, which has brought heavy computation burden.The FFSBM (fast full search block matchin...
An Efficient VLSI Architecture for MC Interpolation in AVC Video Coding
VLSI Architecture MC Interpolation AVC Video Coding
2004/12/31
Video Coding (AVC) has employed a 6-tap interpolation FIR filter in its motion compensation (MC) part for high coding efficiency. But it is accompanied by increasing the complexity in calculation and ...