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Pipeline ADC后台数字校正中传输函数建模算法
后台校正 插值算法 多项式插值
2014/6/20
采用后台校正技术,通过对级间余量放大器传输函数建模来估计误差,以提高流水线型ADC(analog to digital converter, ADC)的性能。为了在校正精度、硬件消耗、功率消耗和算法收敛速度之间做一个合理的权衡,需要在建模时选用一个合理的插值算法。以一个12位,采样频率40兆的流水线型ADC为原型,分别采用分段线性插值、三次多项式插值对第一级余量放大器传输函数建模,用硬件描述语言V...
A HIGHLY EFFICIENT PIPELINE ARCHITECTURE OF RDO-BASED MODE DECISION DESIGN FOR AVS HD VIDEO ENCODER
mode decision RDO, AVS pipeline
2011/6/11
Like H.264, AVS video coding standard also uses macroblock (MB) based motion compensation (MC) and mode decision (MD). Rate distortion optimization (RDO) is the best known mode decision method, but wi...