搜索结果: 1-15 共查到“信息处理技术 VLSI”相关记录17条 . 查询时间(0.064 秒)
VLSI数字信号处理培训成功举办（图）
VLSI 信号处理
2023/8/31
2023年8月17—18日，由深圳市高新技术产业促进中心（国家集成电路设计深圳产业化基地）与工业和信息化部人才交流中心芯动力人才计划共同组织的国际名家讲堂VLSI数字信号处理培训在深圳市南山区软件大厦顺利举办。
针对MPEG的去块效应技术的研究及其VLSI实现
方块效应 区域分类 自适应滤波
2010/11/25
现今随着数据压缩的广泛应用，以及MPEG视频编解码的普遍使用，块效应噪声也随之而来。为了消除块效应、提高视频质量，许多去块效应的算法[2-12]被人们所提出，然而大部分算法的运算量都很大，不适合应用在视频处理芯片上。针对这个问题，H.-S. Kong等人[13]提出了一种新的自适应后处理算法，该算法既能有效消除块效应又大幅度地降低了运算量，然而对图像边缘信息保护不够。本文在H.-S. Kong等人...
Hardware Oriented Algorithm Analysis and Modification for High Definition AVS Video Encoder VLSI Implementation
Hardware Oriented Algorithm Analysis Modification High Definition AVS Video Encoder
2010/6/30
In AVS video coding standard, some algorithms consume huge computation with relatively little coding performance contribution, and some algorithms create data dependencies that are harmful for efficie...
Hardware Oriented Algorithm Analysis and Modification for High Definition AVS Video Encoder VLSI Implementation
Hardware Oriented Algorithm Analysis Modification High Definition AVS Video Encoder
2010/6/30
In AVS video coding standard, some algorithms consume huge computation with relatively little coding performance contribution, and some algorithms create data dependencies that are harmful for efficie...
Efficient Macroblock Pipeline Structure in High Definition AVS Video Encoder VLSI Architecture
Efficient Macroblock Pipeline Structure AVS Video Encoder VLSI Architecture
2010/6/30
In traditional four-stage pipeline structures for H.264 video encoder hardware implementation, rate distortion optimization (RDO) based mode decision was turned off, and
dual-port or ping-pang on-chi...
High Throughput VLSI Architecture for Multiresolution Motion Estimation in High Definition AVS Video Encoder
VLSI Architecture Multiresolution Motion Estimation Video Encoder
2010/6/30
This paper proposes a hardware friendly multiresolution motion estimation algorithm and VLSI architecture for high definition MPEG-like video encoder hardware implementation. By parallel searching and...
基于5/3提升小波变换的心电信号压缩算法及VLSI实现
心电图信号 信号压缩 小波提升变换 FPGA Verilog HDL
2010/6/25
小波变换的应用越来越广泛，但小波变换的硬件实现成为小波变换实时应用的一个关键问题。根据提升小波变换的框架结构，以小波子带系数自适应编码为核心，研究了基于5层5/3提升小波变换及其反变换的ECG信号的压缩算法及其FPGA实现。系统设计采用Verilog HDL语言和流水线设计方法，提高了硬件资源的利用率。系统实现选用Altera 公司CYCLONE EP2C35F672C器件，并采用MITBIH数...
数字电视标准DMB-T高速LDPC译码器VLSI设计
数字电视广播地面传输标准 修正最小和算法 半并行译码器
2009/7/10
在我国的数字电视广播地面传输标准DMB-T中，使用了准循环非规则LDPC码作为前向纠错编码。针对此标准中LDPC码的特点，采用修正最小和译码算法，设计了一种半并行结构实时译码器，可实现DMB-T中三种不同码率下的LDPC译码，并有效地实现了硬件结构复用。与其他设计方案相比较，减少了RAM块的数量一半以上，全局布线难度也大大降低。整个设计在Stratix II FPGA上进行了综合验证。当译码迭代次...
VLSI冗余单元最优分配的遗传算法求解
遗传算法 成品率 备用单元
2009/5/8
随着VLSI芯片面积的增加和电路复杂性的增强,芯片的成品率受制造缺陷影响的概率逐渐增加。为了解决这一问题,人们将容错技术结合入集成电路设计中。要使一个系统具有较强的容错能力,必须给系统提供一定量冗余单元。本文利用遗传算法有效地解决了使系统成品率达到最大的冗余单元最优分配问题。
适合硬件实现的JPEG2000码率控制算法及其VLSI结构设计
图像处理 图像压缩 率控制
2009/1/22
为了简化硬件实现的复杂度和降低存储量，提出一种采用码率预分配的JPEG2000码率控制算法，并给出相应的VLSI结构设计．原始图像经过小波变换和量化后，对EBCOT码块的有效比特平面进行独立熵估计，计算出所有码块的估计熵总和．依据每个码块的估计熵在所有码块的估计熵总和中所占的比例，指导分配每个码块的码率，EBCOT编码器根据分配到的码率实时截断码流和编码通道，减少了T1编码的时间．码块经过T1编码...
A Novel VLSI Architecture of Motion Compensation for Multiple Standards
VLSI Architecture Motion Compensation Multiple Standards
2008/12/31
Motion compensation (MC) is one of the most important technologies capable of removing the temporal redundancy and widely adopted by the main video standards. From the older MPEG-2 to the latest H.264...
An Efficient VLSI Architecture for Motion Compensation of AVS HDTV Decoder
VLSI Architecture Motion Compensation AVS HDTV Decoder
2006/12/31
An Efficient VLSI Architecture for Motion Compensation of AVS HDTV Decoder.
An Efficient VLSI Architecture of VLD for AVS HDTV Decoder
VLSI Architecture VLD AVS HDTV Decoder
2006/12/31
!aIn this paper, we present a VLSI design of Variable Length Code Decoder for AVS video standard. As a co-processor of a RISC CPU, the design can decode Fixed Length Code, unsigned or signed k-th Exp-...
An Implemented VLSI Architecture of Inverse Quantizer for AVS HDTV Video Decoder
VLSI Architecture Inverse Quantizer AVS HDTV Video Decoder
2005/12/31
AVS is Chinese new audio and video coding standard. A pipeline-based architecture of inverse quantizer for AVS video standard is proposed in this paper. Due to using one-pass processing for Run Length...
Improved FFSBM Algorithm and Its VLSI Architecture for Variable Block Size Motion Estimation of H.264,
Improved FFSBM Algorithm VLSI Architecture Variable
2005/12/31
The video coding standard H.264/AVC has adopted variable block size motion estimation to improve coding efficiency, which has brought heavy computation burden.The FFSBM (fast full search block matchin...