搜索结果: 1-9 共查到“信息与通信工程 VLSI Architecture”相关记录9条 . 查询时间(0.095 秒)
Efficient Macroblock Pipeline Structure in High Definition AVS Video Encoder VLSI Architecture
Efficient Macroblock Pipeline Structure AVS Video Encoder VLSI Architecture
2010/6/30
In traditional four-stage pipeline structures for H.264 video encoder hardware implementation, rate distortion optimization (RDO) based mode decision was turned off, and
dual-port or ping-pang on-chi...
High Throughput VLSI Architecture for Multiresolution Motion Estimation in High Definition AVS Video Encoder
VLSI Architecture Multiresolution Motion Estimation Video Encoder
2010/6/30
This paper proposes a hardware friendly multiresolution motion estimation algorithm and VLSI architecture for high definition MPEG-like video encoder hardware implementation. By parallel searching and...
A Novel VLSI Architecture of Motion Compensation for Multiple Standards
VLSI Architecture Motion Compensation Multiple Standards
2008/12/31
Motion compensation (MC) is one of the most important technologies capable of removing the temporal redundancy and widely adopted by the main video standards. From the older MPEG-2 to the latest H.264...
An Efficient VLSI Architecture for Motion Compensation of AVS HDTV Decoder
VLSI Architecture Motion Compensation AVS HDTV Decoder
2006/12/31
An Efficient VLSI Architecture for Motion Compensation of AVS HDTV Decoder.
An Efficient VLSI Architecture of VLD for AVS HDTV Decoder
VLSI Architecture VLD AVS HDTV Decoder
2006/12/31
!aIn this paper, we present a VLSI design of Variable Length Code Decoder for AVS video standard. As a co-processor of a RISC CPU, the design can decode Fixed Length Code, unsigned or signed k-th Exp-...
An Implemented VLSI Architecture of Inverse Quantizer for AVS HDTV Video Decoder
VLSI Architecture Inverse Quantizer AVS HDTV Video Decoder
2005/12/31
AVS is Chinese new audio and video coding standard. A pipeline-based architecture of inverse quantizer for AVS video standard is proposed in this paper. Due to using one-pass processing for Run Length...
Improved FFSBM Algorithm and Its VLSI Architecture for Variable Block Size Motion Estimation of H.264,
Improved FFSBM Algorithm VLSI Architecture Variable
2005/12/31
The video coding standard H.264/AVC has adopted variable block size motion estimation to improve coding efficiency, which has brought heavy computation burden.The FFSBM (fast full search block matchin...
An Efficient VLSI Architecture for MC Interpolation in AVC Video Coding
VLSI Architecture MC Interpolation AVC Video Coding
2004/12/31
Video Coding (AVC) has employed a 6-tap interpolation FIR filter in its motion compensation (MC) part for high coding efficiency. But it is accompanied by increasing the complexity in calculation and ...
An Efficient VLSI Architecture of the Sample Interpolation for MPEG-4 Advanced Simple Profile
Efficient VLSI Architecture the Sample Interpolation MPEG-4 Advanced Simple Profile
2004/12/31
Sample interpolation which has a computationally expensive finite impulse response (FIR) digital filter is one of the key modules in MPEG-4 Advanced Simple Profile (ASP). Normal FIR architectures have...